Dynamic Random Access Memory utilizes capacitors to store bits of information within an integrated circuit. A capacitor is formed by placing a dielectric material between two electrodes formed from conductive materials. A capacitor's ability to hold electrical charge (i.e., capacitance) is a function of the surface area of the capacitor plates A, the distance between the capacitor plates d (i.e. the physical thickness of the dielectric layer), and the relative dielectric constant or k-value of the dielectric material. The capacitance is given by:
                    C        =                              κɛ            0                    ⁢                      A            d                                              (                  Eqn          .                                          ⁢          1                )            where ∈o represents the vacuum permittivity.
The dielectric constant is a measure of a material's polarizability. Therefore, the higher the dielectric constant of a material, the more electrical charge the capacitor can hold. Therefore, for a given desired capacitance, if the k-value of the dielectric is increased, the area of the capacitor can be decreased to maintain the same cell capacitance. Reducing the size of capacitors within the device is important for the miniaturization of integrated circuits. This allows the packing of millions (mega-bit (Mb)) or billions (giga-bit (Gb)) of memory cells into a single semiconductor device. The goal is to maintain a large cell capacitance (generally ˜10 to 25 fF) and a low leakage current (generally <10−7 A cm−2). The physical thickness of the dielectric layers in DRAM capacitors could not be reduced unlimitedly in order to avoid high leakage current caused by tunneling mechanisms, which exponentially increases as the thickness of the dielectric layer decreases.
Traditionally, SiO2 has been used as the dielectric material and semiconducting materials (semiconductor-insulator-semiconductor [SIS] cell designs) have been used as the electrodes. The cell capacitance was maintained by increasing the area of the capacitor using very complex capacitor morphologies while also decreasing the thickness of the SiO2 dielectric layer. Increases of the leakage current above the desired specifications have demanded the development of new capacitor geometries, new electrode materials, and new dielectric materials. Cell designs have migrated to metal-insulator-semiconductor (MIS) and now to metal-insulator-metal (MIM) cell designs for higher performance.
Typically, DRAM devices at technology nodes of 80 nm and below use MIM capacitors wherein the electrode materials are metals. These electrode materials generally have higher conductivities than the semiconductor electrode materials, higher work functions, exhibit improved stability over the semiconductor electrode materials, and exhibit reduced depletion effects. The electrode materials must have high conductivity to ensure fast device speeds. Representative examples of electrode materials for MIM capacitors are metals, conductive metal oxides, conductive metal silicides, conductive metal nitrides (i.e. TiN), or combinations thereof. MIM capacitors in these DRAM applications utilize insulating materials having a dielectric constant, or k-value, significantly higher than that of SiO2 (k=3.9). For DRAM capacitors, the goal is to utilize dielectric materials with k values greater than about 40. Such materials are generally classified as high-k materials. Representative examples of high-k materials for MIM capacitors are non-conducting metal oxides, non-conducting metal nitrides, non-conducting metal silicates or combinations thereof. These dielectrics may also include additional dopant materials.
One class of high-k dielectric materials possessing the characteristics required for implementation in advanced DRAM capacitors are high-k metal oxide materials. Zirconium dioxide (ZrO2) is a metal oxide dielectric material which displays significant promise in terms of serving as a high-k dielectric material for implementation in DRAM capacitors.
Generally, as the dielectric constant of a material increases, the band gap of the material decreases. This leads to high leakage current in the device. As a result, without the utilization of countervailing measures, capacitor stacks implementing high-k dielectric materials may experience large leakage currents. High work function electrodes (e.g., electrodes having a work function of greater than 5.0 eV) may be utilized in order to counter the effects of implementing a reduced band gap high-k dielectric layer within the DRAM capacitor. Metals, such as platinum, gold, ruthenium, and ruthenium oxide are examples of high work function electrode materials suitable for inhibiting device leakage in a DRAM capacitor having a high-k dielectric layer. The noble metal systems, however, are prohibitively expensive when employed in a mass production context. Moreover, electrodes fabricated from noble metals often suffer from poor manufacturing qualities, such as surface roughness, poor adhesion, and form a contamination risk in the fab.
Conductive metal oxides, conductive metal silicides, conductive metal nitrides, or combinations thereof comprise other classes of materials that may be suitable as DRAM capacitor electrodes. Generally, transition metals and their conductive binary compounds form good candidates as electrode materials. The transition metals exist in several oxidation states. Therefore, a wide variety of compounds are possible. Different compounds may have different crystal structures, electrical properties, etc. It is important to utilize the proper compound for the desired application.
Generally, a deposited thin film may be amorphous, crystalline, or a mixture thereof. Furthermore, several different crystalline phases may exist. Therefore, processes (both deposition and post-treatment) must be developed to maximize the formation of the desired crystalline phase and to minimize the presence of unwanted phases. The DRAM electrode materials and dielectric materials may be formed using any common formation technique such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PE-ALD), atomic vapor deposition (AVD), ultraviolet assisted atomic layer deposition (UV-ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD).
The capacitance of a DRAM capacitor can be increased by increasing the area of the capacitor plates as illustrated in Eqn. 1 above. This is a common technique used in the design of MIM capacitor structures and results in structures with severe morphologies. Examples of typical DRAM MIM structures include deep tranches, stacked structures, fin-type structures, crown-type structures, etc. The step coverage (a measure of film thickness uniformity) must be very good for both the electrode materials and the dielectric materials over these severe morphologies. Therefore, ALD, PE-ALD, AVD, UV-ALD, and CVD are preferred methods of deposition of these materials. Advantageously, ALD is a preferred method of deposition.
A disadvantage with most ALD deposition technologies is that the deposition rate of the materials is slow. A typical ALD technology comprises the steps of exposing a surface to a first precursor to form a monolayer of an adsorbed species. The process chamber is then purged and a second reactive gaseous species is introduced into the process chamber to react with the first precursor and form the desired material. The process chamber is then purged again and the cycle is repeated until the desired material thickness is reached. The surface coverage of the monolayer of the first precursor is rarely 100% and the apparent deposition rate per ALD cycle can be less than 0.1 nm per cycle. The apparent deposition rate is calculated by repeating the ALD cycle a number of times and then measuring the resultant film thickness. The slow deposition rate for ALD technologies adds time and expense to the manufacture of DRAM devices.
The use of ZrO2 as a high-k dielectric material in DRAM capacitors is generally paired with the use of TiN as the electrode material. This combination works well because TiN has high conductivity, a high work function (4.7 eV), and does not interact with the ZrO2 to form unwanted interfacial layers. However, the deposition rate of ZrO2 on TiN using ALD technologies is slow (˜0.8 nm/cycle in the case of the ZrMCTA precursor). This adds time and cost to the manufacture of DRAM devices using ZrO2 as the high-k dielectric material and TiN as the electrode material.
Therefore, there is a need to develop methods for improving the deposition rate of a ZrO2 high-k dielectric material in a DRAM capacitor without degrading the performance of the capacitor.